This course is an elective course for part III students of the Bachelor of Engineering.
It is naturally divided in two parts, usually taught by two different lecturers.
In the first part, the study of fundamental concepts in modern computer systems' design and organisation is provided. It starts by introducing the instruction set architecture (ISA) as the boundary between the hardware and software. A subset of MIPS ISA is discussed in detail as a case study, and a quick review in assembly programming is covered. The next topic, high-level implementation of the processor, is studied through the single-cycle, multi-cycle, and pipelined implementations. The advantage of different implementations is examined through performance evaluation techniques.
In the second part the focus is on a bit higher-level parts of the processor architecture. A central role plays the memory architecture and system: the structure and organisation of caches, virtual memory and the memory management unit. The last big topic is then the different forms of processor parallelism, from instruction level to thread level. Cache coherence and memory organisation play a major role for performance for multiprocessor systems and will be studied in detail.